Overview
- Today’s power hungry processors do not meet the demand for “green” technology, and they suffer from high complexity, low interconnect bandwidth, poor memory access, and low scalability. Remarkably, there are no game-changing architectures on the industry’s roadmap. Array is a paradigm shift.
- Array is a suite of proprietary multi-core processor technologies that overcomes the major obstacles facing the state-of-the-art, while delivering an astounding 300 times MIPS/watt performance improvement over the leading multi-core solutions.
- To achieve this remarkable MIPS/watt performance, the industry must adopt numerous fundamental Array Portfolio patent families that will be essential and blocking for decades to come.
Technology and Applications
The Array Portfolio paves the way for unprecedented multi-core performance utilizing homogeneous architecture, inventive means and methods for communicating between the cores and propagating instructions and data throughout the array, and Dual Asynchronicity.
See the Array Portfolio Lifecycle Chart.
| On-Demand Pulse Generator | Each core operates (timing wise) like an organic brain that is not slaved to a clock. A stimulus (an instruction to execute) will cause a response (execution of that instruction). This is superior because: (1) when there is no instruction to be executed, the core will use NO power; and (2) instructions are executed at the native speed of the silicon, rather than being slaved to a clock.This eliminates the need for a master clock, and dramatically reduces power consumption. |
| Homogeneous Architecture | Identical cores means chips utilizing Array Portfolio technologies are easily field-reprogrammable (especially significant for wireless and communications applications), and instantly scalable.In addition, identical cores can share loads on the fly with neighboring cores, resulting in super-low programming complexity. |
| On-Core Memory | On-Core Memory increases speed because it eliminates the need for a Shared Memory, and thus eliminates the inherent bottleneck in other multi-core architectures. |
| Asynchronous Mesh Network | The Asynchronous mesh network increases speed because it eliminates the need for a Shared Bus, and thus eliminates the inherent bottleneck in other multi-core architectures. |
Though multi-core solutions are expected to capture 30% of the processor market by 2012, multi-core competitors such as Intel, Arm, Tilera, and Cavium Networks have solutions designed for specific applications, and fail to address one or more key multi-core design obstacles, such as a single master clock, a shared bus, a shared memory, and heterogeneous architecture.
Array Innovators
Through its IntellaSys division, The TPL Group invested $70M over 4 years in Array Portfolio development and the SEAforth proof of concept processor line. The design team, led by Chuck Moore, renowned processor architect and inventor of MMP Portfolio, comprised 75 engineers, 16 inventors, and was supported by a world-class intellectual property team expert in patenting technology geared towards licensing.