Overview
- An IC “package” provides interconnection and protection for semiconductor die, and is a major cost factor in the ultimate price of an IC.
- Technology evolution on the die has dramatically outpaced the technology evolution of its packaging. Conventional packaging techniques, such as wire bonding, have large footprints, low performance, and high cost relative to the dies packaged within them.
- “Wafer level packaging,” or WLP, revolutionized the process by packaging at the wafer level, rather than after wafer slicing, resulting in a dramatically smaller (true chip size) and thinner footprint results.
- WLP is “green,” since manufacturing complexity is reduced and RoHS plastics are eliminated.
Technology & Applications
Chip Scale Portfolio technologies such as through-silicon via (TSV), Dual Interconnect WLP are enjoying rapid market adoption (see the Chip Scale Portfolio Lifecycle Chart).
| TSV | This packaging technology utilizes conductive passages (vias) to create electrical contacts, and includes Glass TSV, Multi-Level TSV, and Patterned Support TSV solutions.This family of proprietary TSV solutions is ideal for LEDs since it can boost lumen output while reducing materials, manufacturing, testing, storage and shipping costs, in addition to enabling non-conventional light treatments and directional changes such as beam focusing and edge emission.
TSV is also ideal for non-optical MEMS devices such as microphones, accelerometers, and gyroscopes. |
| Dual Interconnect | The hybrid Dual Interconnect solution provides separate optimal paths for high speed and low speed signals by combining the benefits of closely-spaced TSV with a large cross-sectional “Wrap Around” connection, which is important for significant peak current carrying capability. Dual interconnect design minimizes overall die area and PCB real estate, while increasing yield and reliability. |
Since 2007 every major image sensor manufacturer has announced its intention to use WLP.
Major growth areas include: NOR and NAND Flash driven by cell phones and SSDs, DRAM driven by server modules and PCs, MEMS devices driven by audio sensors, inertials, RF and optical applications, as well as 3D SIP Logic driven by FPGAs, CPUs, MCUs and analog parts. By 2014, industry analysts predict voracious adoption of WLP processes of 50 to 100 times 2008 rates.
Chip Scale Innovators
Dr. Jürgen Leib initiated the TSV activities at Schott AG, targeting advanced wafer-level sensor packaging technologies for automotive, medical and MEMS. With a subsequent focus on image sensors, the technology was brought to production at Schott Advanced Packaging Singapore in 2005, where Dr. Leib served as CTO. In 2006, Dr. Leib co-founded the MSG Lithoglas AG to act as consultant for Fraunhofer IZM on 3D-TSV developments. Dr. Leib is member of the Germany Physical Society (DGP) and IEEE CPMT.